Feedback voltage DC level cancelling for configurable output DC-DC switching converters

ABSTRACT

A system is disclosed which provides feedback voltage DC level cancelling for a configurable output of a DC-DC switching converter. By simplifying the design, the operational amplifier can be used for a wider output voltage range. Extension of the usage case to a Boost DC-DC switching converter can give noticeable performance improvements. Offset introduction using a flying capacitor is attractive because it does not require trimming. The proposal also allows for improvements for DC-DC switching converters designed for lower supply voltages, with no decrease in the differential input signal swing.

BACKGROUND Field

The disclosure relates generally to feedback voltage in DC-DC switchingconverters.

Description of Related Art

DC-DC switching converters such as Buck switching converters, Buck-Boostswitching converters, and Boost switching converters are basic buildingblocks of power management systems.

FIG. 1 illustrates basic topology 100 of a DC-DC switching converter, ofthe prior art. Supply voltage VDAC 110 and output voltage VOUT 180supply the inverting and non-inverting inputs respectively, of ErrorAmplifier 120. Error Amplifier 120 provides the input to Error Amp Dist140, where the output of Error Amp Dist 140 and Ramp gen 130 supply theinputs to Pulse-width modulation (PWM) Logic 150. The output of PWMLogic 150 supplies input signals to logic LXIA Logic 155, where LXIALogic 155 includes current sensing, positive and negative currentlimits, and high-side device 160 and low-side device 170, whichdetermine output voltage VOUT 180, across inductor LX1A.

FIG. 2 shows example 200 of a DC-DC switching converter, with a widerinput and output voltage range, of the prior art. In this case, theinput to supply voltage VDAC 110 and output voltage VOUT 180, onfeedback FB, can range from 0.3V to 2.2V. A PMOS input device pairserves as inputs to Error Amplifier 120, across which a wider input andoutput voltage range is required. Error Amplifier 120 provides the inputto Error Amp Dist 140, and Error Amp Dist 140 and Ramp gen 130 supplythe inputs to Pulse-width modulation (PWM) Logic 150.

The example of FIG. 2 may be improved by modifying the error amplifier,but there are limitations of its practice. To reduce costs, the use oflow voltage transistors is minimized, along with the resultingarchitecture. In addition, the compensation circuitry of the erroramplifier, including functionality to support practical power managementproducts, increases complexity. The wider input range required on thesupply voltage makes it difficult to maintain a constanttransconductance, affecting loop stability at worst case. As a result,power consumption and silicon area increase.

SUMMARY

An object of the disclosure is to provide a DC-DC switching converteroffset circuit, for DC level cancelling in a DC-DC switching converter.

Further, another object of this disclosure is to support a wide outputvoltage range on a feedback error amplifier, of the DC-DC switchingconverter offset circuit.

Still another object of the disclosure is to provide a flexible currentgain for the output voltage, of a DC-DC switching converter.

Still another object of the disclosure is to implement the voltageoffset using a switching capacitor circuit, sampling the input of theerror amplifier on an intermediate capacitor, and using AC coupling toadd an offset voltage.

To accomplish the above and other objects, a DC-DC switching converteroffset circuit is disclosed, comprised of a VDAC, configured to providea supply voltage and a reference voltage. The DC-DC switching converteroffset circuit is further comprised of a difference circuit, configuredto provide an offset voltage from the output feedback voltage and thereference voltage. The DC-DC switching converter offset circuit isfurther comprised of an error amplifier circuit, configured to receivethe offset voltage and the reference voltage, and a voltage to currentconversion circuit, configured to provide a flexible current gain.

The above and other objects are further achieved by a method forfeedback voltage DC level cancelling for configurable output DC-DCswitching converters. The steps include providing a voltage offset tothe feedback error amplifier of a DC-DC switching converter. Supportinga wide output voltage range for the DC-DC switching converter isprovided. A flexible current gain for a higher output voltage isprovided. Implementing the voltage offset using a switching capacitorcircuit, sampling the input of the error amplifier on an intermediatecapacitor, and using AC coupling to add an offset voltage is provided.

In various embodiments the function may be achieved by implementing aBuck, Buck-Boost, or Boost DC-DC switching converter.

In various embodiments the function may be achieved by implementingfeedback voltage DC level cancelling for a single phase DC-DC switchingconverter.

In various embodiments the function may be achieved by implementingfeedback voltage DC level cancelling for a multiple phase DC-DCswitching converter.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a basic topology of a DC-DC switching converter, ofthe prior art.

FIG. 2 shows an example of a DC-DC switching converter, with a widerinput and output voltage range, of the prior art.

FIG. 3 illustrates a block diagram of the feedback voltage DC levelcancelling, for a single phase configurable output DC-DC switchingconverter, embodying the principles of the disclosure.

FIG. 4 shows a circuit diagram implementation, using a switchedcapacitor type offset circuit topology for a multiple phase configurableoutput DC-DC switching converter, embodying the principles of thedisclosure.

FIG. 5 illustrates an example of the operation of the feedback voltageoffset, embodying the principles of the disclosure.

FIG. 6 illustrates an example of Phase 1 operation of the feedbackvoltage offset, embodying the principles of the disclosure.

FIG. 7 illustrates an example of Phase 2 operation of the feedbackvoltage offset, embodying the principles of the disclosure.

FIG. 8 shows a simulation of a Buck DC-DC switching converter with asingle phase, where VDAC=0.982V and no offset function is used.

FIG. 9 shows a simulation of a Buck DC-DC switching converter with asingle phase, where VDAC=0.982V and a 0.5V offset function is used.

FIG. 10 shows a simulation of a Buck DC-DC switching converter withsingle phase, where VDAC=0.982V and a 1.0V offset function is used.

FIG. 11 shows a simulation of a Buck DC-DC switching converter withsingle phase, where VDAC=0.982V and a 1.0V offset function is used, withan additional current gain of 1.1.

FIG. 12 is flow chart of a method for feedback voltage DC levelcancelling, for configurable output DC-DC switching converters,embodying the principles of the disclosure.

DETAILED DESCRIPTION

There are several alternatives, for feedback voltage DC levelcancelling, when using a Buck DC-DC switching converter, including arail-to-rail amplifier and a resistive divider. For a Boost DC-DCswitching converter, a resistive divider is the most likely alternative.The disclosure will give significant advantages, including improvementof the standby current of the switching converter, and a higher systemperformance, where the output voltage is higher than any other availablepower rail in the system.

FIG. 3 illustrates block diagram 300 of feedback voltage DC levelcancelling, for a single phase configurable output DC-DC switchingconverter, embodying the principles of the disclosure. Voltage digitalto analog converter VDAC 310 and output voltage VOUT 380 provide offsetVOUT-VCM to the non-inverting input of Error Amplifier 320. VDAC 310supplies reference voltage VCM to the inverting input of Error Amplifier320, and error amplifier output EA_OUT, 1.8V, supplies the input toError Amp Dist 340, which distributes the voltage to current conversionand provides a flexible current gain. Error Amp Dist 340 and Ramp gen330 supply the inputs to Pulse-width modulation (PWM) Logic 350, wherePWM Logic 350 includes high-side device 360 and low-side device 370, andoutput voltage VOUT 380 across inductor LX1A.

A flexible current gain moves the output of error amplifier higher orlower, supplying a higher or lower output voltage. In this way, thecurrent gain helps optimize the overall voltage range of the switchingconverter.

Additional difference circuitry can be added to the offset to support awider output voltage range, when a switched capacitor type offsetcircuit topology is used. The input of the error amplifier may besampled on an intermediate capacitor, and arrive exponentially to a holdcapacitor. By means of AC coupling, an offset is exponentially added tothe input of the error amplifier, and a feedback voltage penetratescontinuously, minimizing any phase delay.

FIG. 4 shows circuit diagram implementation 400, using a switchedcapacitor type offset circuit topology for a multiple phase configurableoutput DC-DC switching converter, embodying the principles of thedisclosure. The output voltage of the DC-DC switching converter isfeedback voltage FB, across capacitor C1, supplying the non-invertinginput of error amplifier O1. The voltage on resistive divider R3-R1-R2supplies the inverting input of error amplifier O1.

The sampled feedback voltage transmits to amplifier O1 in one cycle, andthe value on intermediate capacitor C2 exponentially arrives to holdcapacitor C1. In this way, the offset applied to the feedback voltage isadded through the AC coupling of capacitors C1 and C2.

Sampling of feedback voltage FB may create a phase delay, and affect theload line transition specification. In practice, a wider output voltagerange can cause the error amplifier to become less than ideal overprocess, temperature, and supply conditions. A faster sampling time forthe feedback voltage will improve these conditions, and minimize anyphase shift.

FIG. 5 illustrates example 500 operation of the feedback voltage offset,embodying the principles of the disclosure. Switch EN is open when thefeedback voltage offset function is enabled, and closed when thefeedback voltage offset function is disabled. When the feedback voltageoffset is operating in Phase 1, switch P1 is closed, and when thefeedback voltage offset is operating in Phase 2, switch P2 is closed.The output voltage of the switching converter is feedback voltage FB,and the VDAC voltage may be trimmed, with a method known in the priorart, when setting the offset voltage.

The Phase 1 and Phase 2 are non-overlapped clock timings, and thefrequency will depend on the load transition specification. Practically,a frequency larger than the loop switching frequency is required, andthe system clocks may be two to four times faster than the switchingfrequency of the loop. A faster sampling time will improve any delayintroduced by the phases.

When Phase 1 switch P1 is closed, feedback voltage FB charges capacitorC1, providing reference voltage VREF to the input of VDAC. When Phase 2switch P2 is closed, capacitor C1 couples with capacitor C2, todetermine the offset of the feedback voltage on the non-inverting inputof the error amplifier. The VDAC output voltage supplies the input ofthe inverting input of the error amplifier.

FIG. 6 illustrates example 600, Phase 1 operation of the feedbackvoltage offset, embodying the principles of the disclosure. Capacitor C1samples the feedback voltage FB, from the output voltage of the DC-DCswitching converter, providing the reference voltage VREF to the inputof VDAC. The voltage difference, VOUT-VREF, when both P1 and enableswitch ENI are closed, is charged across C1.

FIG. 7 illustrates example 700, Phase 2 operation of the feedbackvoltage offset, embodying the principles of the disclosure. When both P2and enable switch ENI are closed, the charge on capacitor C1 transfersto C2. The voltage on capacitor C2 becomes((C1*C2)/(C1+C2))*(VOUT−VREF), where voltage VOUT-VREF is thenon-inverting input of the error amplifier.

The disclosure works to provide a relaxation of the error amplifierdesign, using existing components to avoid complexity. Capacitor sizeand sampling frequency determine the transient response. The switchedcapacitor offset circuit is adjustable, where the resistive dividerprovides a flexible current gain. The offset circuit can increase theoutput voltage range, without error amplifier limitation, until anoutput DC limit is reached. A constant transconductance and currentconsumption is maintained, reducing overall power consumption.

FIGS. 8-11 show test cases based on a Buck DC-DC switching converterwith a single phase, as illustrated in the block diagram of FIG. 3. Notethat the offset function can add both positive offset, as shown in FIGS.9-11, and negative offset. The conditions are for VDDA=3.3V, VX (passdevice)=3.7V, nominal process, room temperature, and switching frequencyfsw=3 MHz. The offset circuit uses the same clock as the control clock,and could be different, to allow some flexibility in the clock scheme.

FIG. 8 shows simulation 800, of a Buck DC-DC switching converter with asingle phase, where VDAC=0.982V and no offset function is used. In thiscase, input to the Error Amplifier, VDAC_OUT 820, is 0.982V. The outputof the Error Amplifier, EA_OUT 830, is 1.610V, supplying Error Amp Distand PWM logic. The output of Ramp gen, RAMP_GEN 840, is 1.587V, and VOUT810 is 0.982V.

FIG. 9 shows simulation 900, of a Buck DC-DC switching converter with asingle phase, where VDAC=0.982V and a 0.5V offset function is used. Inthis case, input to the Error Amplifier, VDAC_OUT 920, is 0.982V. Theoutput of the Error Amplifier, EA_OUT 930, is 1.717V, supplying ErrorAmp Dist and PWM logic. The output of Ramp gen, RAMP_GEN 940, is 1.739V,and VOUT 910 is 1.483V. Simulation 900 illustrates how the offsetcircuit works properly without any VDAC control loop setting change.

FIG. 10 shows simulation 1000, of a Buck DC-DC switching converter witha single phase, where VDAC=0.982V and a 1.0V offset function is used. Inthis case, input to the Error Amplifier, VDAC_OUT 1020, is 0.982V. Theoutput of the Error Amplifier, EA_OUT 1030, is 1.825V, supplying ErrorAmp Dist and PWM logic. The output of Ramp gen, RAMP_GEN 1040, is1.763V, and VOUT 1010 is 1.982V. Simulation 1000 illustrates how theoffset circuit works properly without any VDAC control loop settingchange.

FIG. 11 shows simulation 1100, of a Buck DC-DC switching converter witha single phase, where VDAC=0.982V and a 1.0V offset function is used,with an additional current gain of 1.1. In this case, input to the ErrorAmplifier, VDAC_OUT 1120, is 0.982V. The output of the Error Amplifier,EA_OUT 1130, is 1.565V, supplying Error Amp Dist and PWM logic. Theoutput of Ramp gen, RAMP_GEN 1140, is 1.849V, and VOUT 1010 is 1.982V.FIG. 11 is has the same conditions as FIG. 10, except for the additionalcurrent gain of 1.1. The voltage to current conversion of Error Amp Disthelps control the Error Amplifier output voltage, adding flexibility tothe design. As a result, the error amplifier output is shifted down from1.825V to 1.565V.

FIG. 12 is flow chart 1200, for a method for feedback voltage DC levelcancelling, for configurable output DC-DC switching converters,embodying the principles of the disclosure. Step 1210 shows providing afeedback error amplifier for a DC-DC switching converter. Step 1220shows supporting a wide output voltage range on the feedback erroramplifier. Step 1230 shows providing a flexible current gain for ahigher output voltage on the DC-DC switching converter. Step 1240 showsimplementing a voltage offset using a switching capacitor circuit,sampling the input of the error amplifier on an intermediate capacitor,and using AC coupling to add the offset voltage.

The advantages of one or more embodiments of the present disclosureinclude the use of conventional DC-DC switching converter architecturetargeted to 0.3V-1.5V for the output voltage range, increasing the rangewithout modification to the control loop. The proposal also allows forimproved switching, optimizing the input voltage range supplied to asimplified error amplifier circuit. A constant performance is maintainedand stability improved, with no change in the differential input signalswing.

While this invention has been particularly shown and described withreference to the preferred embodiments thereof, it will be understood bythose skilled in the art that various changes in form and details may bemade without departing from the spirit and scope of the invention.

The invention claimed is:
 1. A DC-DC switching converter circuit,comprising: a voltage digital to analog converter, VDAC, configured toprovide a VDAC voltage determined by a reference voltage; a differencecircuit, comprising a switched capacitor type offset circuit, configuredto provide an offset voltage determined by a difference between anoutput feedback voltage and said VDAC voltage; and an error amplifiercircuit, configured to receive said offset voltage on a non-invertinginput, and said VDAC voltage on an inverting input, wherein said outputfeedback voltage is transmitted to said error amplifier circuit in onecycle and said output feedback voltage on an intermediate capacitor isconfigured to exponentially arrive to a hold capacitor within saidswitched capacitor type offset circuit.
 2. The DC-DC switching convertercircuit of claim 1, wherein said DC-DC switching converter is configuredfor a single phase.
 3. The DC-DC switching converter circuit of claim 1,wherein a resistive divider is configured to generate said VDAC voltageto said error amplifier circuit.
 4. The DC-DC switching convertercircuit of claim 1, wherein said offset voltage is added to said outputfeedback voltage through an AC coupling of said intermediate capacitorand said hold capacitor.
 5. The difference circuit of claim 1, whereinsaid switched capacitor type circuit comprises an intermediate capacitorand a hold capacitor, wherein said intermediate capacitor is configuredwith a voltage difference between said output feedback voltage and saidreference voltage during a first switching period, and said holdcapacitor is configured to have said voltage difference transferred toit during a second switching period.
 6. The DC-DC switching convertercircuit of claim 1, wherein said DC-DC switching converter comprises aBuck, Buck-Boost, or Boost switching converter.
 7. The DC-DC switchingconverter circuit of claim 1, wherein said DC-DC switching converter isconfigured to increase an range of the output feedback voltage.
 8. TheDC-DC switching converter circuit of claim 1, wherein said DC-DCswitching converter is configured to decrease an range of an inputvoltage.
 9. The DC-DC switching converter circuit of claim 1, whereinsaid DC-DC switching converter is configured to maintain constanttransconductance.
 10. The DC-DC switching converter circuit of claim 1,wherein a voltage to current conversion circuit, connected at an outputof said error amplifier circuit, is configured for a current gain.
 11. Amethod for feedback voltage DC level cancelling, for configurable outputDC-DC switching converters, comprising: providing a voltage digital toanalog converter, VDAC, voltage determined by a reference voltage;providing an offset voltage, determined by a difference between anoutput feedback voltage and said VDAC voltage, with a difference circuitcomprising a switched capacitor type offset circuit; and receiving saidoffset voltage on a non-inverting input, and said VDAC voltage on aninverting input, with an error amplifier circuit, wherein said outputfeedback voltage transmits to said error amplifier circuit in one cycle,and said output feedback voltage on an intermediate capacitorexponentially arrives to a hold capacitor within said switched capacitortype offset circuit.
 12. The method of claim 11, wherein said DC-DCswitching converter operates with a single phase.
 13. The method ofclaim 11, wherein said offset voltage adds to said output feedbackvoltage through an AC coupling of said intermediate capacitor and saidhold capacitor.